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Intel(R) PXA255 Processor
Electrical, Mechanical, and Thermal Specification
Data Sheet
Product Features

High Performance Processor -- Intel(R) XScaleTM Microarchitecture -- 32 KB Instruction Cache -- 32 KB Data Cache -- 2 KB "mini" Data Cache -- Extensive Data Buffering Intel(R) Media Processing Technology -- Enhanced 16-bit Multiply -- 40-bit Accumulator Flexible Clocking -- CPU clock from 100 to 400 MHz -- Flexible memory clock ratios -- Frequency change modes Rich Serial Peripheral Set -- AC97 Audio Port -- I2S Audio Port -- USB Client Controller -- High Speed UART -- Second UART with flow control -- UART with hardware flow control -- FIR and SIR infrared comm ports

Low Power -- Less than 500 mW Typical Internal Dissipation -- Supply Voltage may be Reduced to 1.00 V -- Low Power/Sleep Modes High Performance Memory Controller -- Four Banks of SDRAM - up to 100 MHz -- Five Static Chip Selects -- Support for PCMCIA or Compact Flash -- Companion Chip interface Additional Peripherals for system connectivity -- Multimedia Card Controller (MMC) -- SSP Controller -- Network SSP controller for baseband -- I2C Controller -- Two Pulse Width Modulators (PWMs) -- All peripheral pins double as GPIOs Hardware debug features Hardware Performance Monitoring features
Order Number: 278805-002
February, 2004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The PXA255 processor EMTS Data Sheet may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2004 *Other names and brands may be claimed as the property of others.
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Data Sheet
PXA255 Processor -- Electrical, Mechanical, and Thermal Specification
Contents
1.0 2.0 3.0 About This Document ............................................................................................ 7 Functional Overview ..............................................................................................7 Package Information ..............................................................................................8 3.1 3.2 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Package Introduction..................................................................................... 8 3.1.1 Functional Signal Definitions ............................................................8 3.1.1.1 PXA255 Processor Signal Pin Descriptions .....................8 Package Power Ratings ..............................................................................22 Absolute Maximum Ratings......................................................................... 22 Power Consumption Specifications ............................................................. 23 Operating Conditions................................................................................... 25 Targeted DC Specifications......................................................................... 26 Targeted AC Specifications ......................................................................... 27 Oscillator Electrical Specifications............................................................... 28 4.6.1 32.768-kHz Oscillator Specifications .............................................. 28 4.6.2 3.6864 MHz Oscillator Specifications .............................................29 Reset and Power AC Timing Specifications ................................................30 4.7.1 Power-On Timing ...........................................................................30 4.7.2 Hardware Reset Timing.................................................................. 32 4.7.3 Watchdog Reset Timing .................................................................32 4.7.4 GPIO Reset Timing ........................................................................32 4.7.5 Sleep Mode Timing ........................................................................33 Memory Bus and PCMCIA AC Specifications .............................................35 Peripheral Module AC Specifications ..........................................................37 4.9.1 LCD Module AC Timing.................................................................. 37 4.9.2 SSP Module AC Timing.................................................................. 37 4.9.3 Boundary Scan Test Signal Timings .............................................. 38 AC Test Conditions .....................................................................................39
Electrical Specifications ...................................................................................... 22
4.8 4.9
4.10
Data Sheet
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PXA255 Processor -- Electrical, Mechanical, and Thermal Specification
Figures
1 2 3 4 5 6 7 8 9 Processor Block Diagram...................................................................................... 8 PXA255 processor .............................................................................................. 19 Power-On Reset Timing ...................................................................................... 31 Hardware Reset Timing ...................................................................................... 32 GPIO Reset Timing ............................................................................................. 33 Sleep Mode Timing ............................................................................................. 34 LCD AC Timing Definitions ................................................................................. 37 SSP AC Timing Definitions ................................................................................. 38 AC Test Load ...................................................................................................... 39
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Related Documentation......................................................................................... 7 Processor Pin Types ............................................................................................. 9 Pin and Signal Descriptions for the PXA255 Processor........................................ 9 Pin Description Notes.......................................................................................... 18 PXA255 processor 256-Lead 17x17mm mBGA Pinout -- Ballpad No. Order .... 20 JA and Maximum Power Ratings........................................................................ 22 Absolute Maximum Ratings ................................................................................ 23 Power Consumption Specifications for PXA255 processor ................................ 24 Voltage, Temperature, and Frequency Electrical Specifications......................... 25 Standard Input, Output, and I/O Pin DC Operating Conditions ........................... 26 Standard Input, Output, I/O Pin DC Operating Conditions for 2.5-V Memory ..... 27 Standard Input, Output, and I/O Pin AC Operating Conditions ........................... 28 32.768-kHz Oscillator Specifications................................................................... 28 3.6864-MHz Oscillator Specifications ................................................................. 29 Power-On Timing Specifications ......................................................................... 31 Hardware Reset Timing Specifications ............................................................... 32 GPIO Reset Timing Specifications ...................................................................... 33 Sleep Mode Timing Specifications ...................................................................... 34 SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications.................... 35 Variable Latency I/O Interface AC Specifications ............................................... 35 Card Interface (PCMCIA or Compact Flash) AC Specifications ......................... 36 Synchronous Memory Interface AC Specifications 1 .......................................... 36 LCD AC Timing Specifications ............................................................................ 37 SSP AC Timing Specifications ............................................................................ 38 Boundary Scan Test Signal Timing ..................................................................... 38
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Data Sheet
PXA255 Processor -- Electrical, Mechanical, and Thermal Specification
Revision History
Date March 2003 February 2004 Revision -001 -002 First public release of the EMTS Updated 400 MHz Idle mode power. Description
Data Sheet
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PXA255 Processor -- Electrical, Mechanical, and Thermal Specification
6
Data Sheet
About This Document
1.0
About This Document
This is the electrical, mechanical, and thermal specification data sheet for the Intel(R) PXA255 Processor. This data sheet contains a functional overview, mechanical data, package signal locations, targeted electrical specifications (simulated), and bus functional waveforms. Detailed functional descriptions other than parametric performance is published in the Intel(R) PXA255 Processor Developer's Manual. Refer to Table 1, "Related Documentation" for a list of documents that support the PXA255 processor.
Table 1.
Related Documentation
Document Title Intel(R) PXA255 Processor Developer's Manual Intel(R) XScale Microarchitecture for the PXA250 and PXA210 Applications Processors Developer's Manual Intel(R) PXA255 Processor Design Guide
TM
Order / Contact 278693 278525 278694
2.0
Functional Overview
The PXA255 processor provides high integration, high performance and low power consumption for portable handheld and handset devices. These processors incorporate the Intel(R) XScaleTM Microarchitecture based on the ARM* V5TE architecture. Refer to the Intel(R) XScaleTM Microarchitecture for the Intel(R) PXA250 and PXA210 Applications Processors User's Manual for implementation details, extensions, and options implemented by the XScale microarchitecture. The processor memory interface supports a variety of memory types that allow flexible design requirements. Hooks for connection to two companion chips permit glueless connection to external devices. An integrated LCD display controller supports displays and permits 1, 2, and 4-bit grayscale, and 8- or 16-bit color pixels. A 256-byte palette RAM provides flexible color mapping capabilities. A rich set of serial devices as well as general-system resources provide enough compute and connectivity capability for many applications. For details on the programming model and theory of operation of each of these units, refer to the Intel(R) PXA255 Processor Developer's Manual. For the processor block diagram, refer to Figure 1, "Processor Block Diagram" on page 8.
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
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Package Information
Figure 1. Processor Block Diagram
RTC OS Timer PWM(2) Int. Controller Clocks & Power Man. General Purpose I/O I2S I2C AC97 UARTs NSSP Slow IrDA Fast IrDA SSP USB Client MMC
Color or Grayscale LCD Controller
Memory Controller
DMA Controller and Bridge
Peripheral Bus
System Bus
Variable Latency I/O Control PCMCIA & CF Control Dynamic Memory Control Static Memory Control
ASIC
XCVR
Socket 0 Socket 1
Intelfi XScale Microarchitecture
SDRAM/ SMROM 4 banks ROM/ Flash/ SRAM 4 banks
3.6864 MHz Osc
32.768 KHz Osc
3.0
3.1
Package Information
Package Introduction
The PXA255 processor is offered in a 256-pin mBGA (refer to Figure 2, "PXA255 processor" on page 19).
3.1.1
3.1.1.1
Functional Signal Definitions
PXA255 Processor Signal Pin Descriptions
Table 3, "Pin and Signal Descriptions for the PXA255 Processor" on page 9 describes the signal definitions for the PXA255 processor. Figure 2, "PXA255 processor" on page 19 illustrates the physical characteristics of the PXA255 processor. Table 5, "PXA255 processor 256-Lead 17x17mm mBGA Pinout -- Ballpad No. Order" on page 20 describes the pinout for the PXA255 processor.
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Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
Package Information
Some of the processor pins can be connected to multiple signals. The GAFRn_m registers determine the signal connected to the pin. Some signals can go to multiple pins. The signal must be routed to one pin only by using the GAFRn_m registers. Because this is true, some pins are listed twice--once in each unit that can use the pin. Not all peripherals can be used simutaneously in one design because different peripherals share the same pins. Table 2. Processor Pin Types
Type IC OC OCZ ICOCZ IA OA IAOA SUP CMOS input CMOS output CMOS output, Hi-Z CMOS bidirectional, Hi-Z Analog Input Analog output Analog bidirectional Supply pin (either VCC or VSS) Function
Table 3.
Pin Name
Pin and Signal Descriptions for the PXA255 Processor (Sheet 1 of 9)
Type Signal Descriptions Reset State Sleep State
Memory Controller Pins MA[25:0] MD[15:0] MD[31:16] nOE nWE OCZ ICOCZ ICOCZ OCZ OCZ Memory address bus. (output) Signals the address requested for memory accesses. Memory data bus. (input/output) Lower 16 bits of the data bus. Memory data bus. (input/output) Used for 32-bit memories. Memory output enable. (output) Connect to the output enables of memory devices to control data bus drivers. Memory write enable. (output) Connect to the write enables of memory devices. SDRAM CS for banks 3 through 0. (output) Connect to the chip select (CS) pins for SDRAM. For the PXA255 processor processor nSDCS0 can be Hi-Z, nSDCS1-3 cannot. SDRAM DQM for data bytes 3 through 0. (output) Connect to the data output mask enables (DQM) for SDRAM. SDRAM RAS. (output) Connect to the row address strobe (RAS) pins for all banks of SDRAM. SDRAM CAS. (output) Connect to the column address strobe (CAS) pins for all banks of SDRAM. Synchronous Static Memory clock enable. (output) Connect to the CKE pins of SMROM. The memory controller provides control register bits for de-assertion. Driven Low Hi-Z Hi-Z Driven High Driven High Driven Low Driven Low Driven Low Note [4] Note [4]
nSDCS[3:0]
OCZ
Driven High
Note [5]
DQM[3:0] nSDRAS nSDCAS SDCKE[0]
OCZ OCZ OCZ OC
Driven Low Driven High Driven High Driven Low
Driven Low Driven High Driven High Driven Low
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
9
Package Information
Table 3.
Pin Name
Pin and Signal Descriptions for the PXA255 Processor (Sheet 2 of 9)
Type Signal Descriptions SDRAM and/or Synchronous Static Memory clock enable. (output) Connect to the clock enable pins of SDRAM. It is deasserted during sleep. SDCKE[1] is always de-asserted upon reset. The memory controller provides control register bits for de-assertion. Synchronous Static Memory clock. (output) Connect to the clock (CLK) pins of SMROM. It is driven by either the internal memory controller clock, or the internal memory controller clock divided by 2. At reset, all clock pins are free running at the divide-by-2 clock speed and may be turned off via free-running control register bits in the memory controller. The memory controller also provides control register bits for clock division and deassertion of each SDCLK pin. SDCLK[0] control register assertion bit defaults to on if the boot-time static memory bank 0 is configured for SMROM. SDRAM Clocks (output) Connect SDCLK[1] and SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1 and 2/3, respectively. They are driven by either the internal memory controller clock, or the internal memory controller clock divided by 2. At reset, all clock pins are free running at the divide-by-2 clock speed and may be turned off via free-running control register bits in the memory controller. The memory controller also provides control register bits for clock division and de-assertion of each SDCLK pin. SDCLK[2:1] control register assertion bits are always de-asserted upon reset. Driven Low Driven Low Reset State Sleep State
SDCKE[1]
OC
Driven low
Driven low
SDCLK[0]
OC
SDCLK[1]
OCZ
SDCLK[2]
OC
Driven Low
Driven Low
nCS[5]/ GPIO[33] nCS[4]/ GPIO[80] nCS[3]/ GPIO[79] nCS[2]/ GPIO[78] nCS[1]/ GPIO[15] nCS[0] RD/nWR RDY/ GPIO[18]
ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ OCZ ICOCZ Static chip select 0. (output) Chip select for the boot memory. nCS[0] is a dedicated pin. Read/Write for static interface. (output) Signals that the current transaction is a read or write. Variable latency I/O ready pin. (input) Notifies the memory controller when an external bus device is ready to transfer data. LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. ICOCZ Memory controller alternate bus master request. (input) Allows an external device to request the system bus from the memory controller. Driven High Driven Low Pulled High Note[1] Note [4] Holds last state Note [3] Static chip selects. (output) Chip selects to static memory devices such as ROM and Flash. Individually programmable in the memory configuration registers. nCS[5:0] can be used with variable latency I/O devices. Pulled High Note[1] Note [4]
L_DD[8]/ GPIO[66]
Pulled High Note[1]
Note [3]
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Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
Package Information
Table 3.
Pin Name L_DD[15]/ GPIO[73] MBGNT/ GP[13] MBREQ/ GP[14]
Pin and Signal Descriptions for the PXA255 Processor (Sheet 3 of 9)
Type Signal Descriptions LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. Memory controller grant. (output) Notifies an external device that it has been granted the system bus. Memory controller grant. (output) Notifies an external device that it has been granted the system bus. Memory controller alternate bus master request. (input) Allows an external device to request the system bus from the memory controller. Reset State Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Sleep State
ICOCZ
Note [3]
ICOCZ ICOCZ
Note [3] Note [3]
PCMCIA/CF Control Pins nPOE/ GPIO[48] nPWE/ GPIO[49] nPIOW/ GPIO[51] nPIOR/ GPIO[50] nPCE[2]/ GPIO[53] nPCE[1]/ GPIO[52] nIOIS16/ GPIO[57] nPWAIT/ GPIO[56] ICOCZ PCMCIA output enable. (output) Reads from PCMCIA memory and to PCMCIA attribute space. PCMCIA write enable. (output) Performs writes to PCMCIA memory and to PCMCIA attribute space. Also used as the write enable signal for variable latency I/O. PCMCIA I/O write. (output) Performs write transactions to PCMCIA I/O space. PCMCIA I/O read. (output) Performs read transactions from PCMCIA I/O space. PCMCIA card enable 2. (output) Selects a PCMCIA card. nPCE[2] enables the high byte lane and nPCE[1] enables the low byte lane. MMC clock. (output) Clock signal for the MMC controller. ICOCZ PCMCIA card enable 1. (outputs) Selects a PCMCIA card. nPCE[2] enables the high byte lane and nPCE[1] enables the low byte lane. IO Select 16. (input) Acknowledge from the PCMCIA card that the current address is a valid 16 bit wide I/O address. PCMCIA wait. (input) Driven low by the PCMCIA card to extend the length of the transfers to/from the PXA255 processor processor. PCMCIA socket select. (output) Used by external steering logic to route control, address, and data signals to one of the two PCMCIA sockets. When PSKTSEL is low, socket zero is selected. When PSKTSEL is high, socket one is selected. Has the same timing as the address bus. PCMCIA register select. (output) Indicates that the target address on a memory transaction is attribute space. Has the same timing as the address bus. Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Note [5] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Note [5]
ICOCZ
Note [5]
ICOCZ ICOCZ
Note [5] Note [5]
ICOCZ
Note [5]
ICOCZ
Note [5]
ICOCZ
Note [5]
PSKTSEL/ GPIO[54]
ICOCZ
Pulled High Note[1]
Note [5]
nPREG/ GPIO[55]
ICOCZ
Pulled High Note[1]
Note [5]
LCD Controller Pins L_DD(7:0)/ GPIO[65:58] L_DD[8]/ GPIO[66] ICOCZ LCD display data. (outputs) Transfers pixel information from the LCD Controller to the external LCD panel. LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. ICOCZ Memory controller alternate bus master request. (input) Allows an external device to request the system bus from the Memory Controller. Pulled High Note[1] Note [3]
Pulled High Note[1]
Note [3]
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
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Package Information
Table 3.
Pin Name L_DD[9]/ GPIO[67]
Pin and Signal Descriptions for the PXA255 Processor (Sheet 4 of 9)
Type Signal Descriptions LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. MMC chip select 0. (output) Chip select 0 for the MMC controller. LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. MMC chip select 1. (output) Chip select 1 for the MMC controller. LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. MMC clock. (output) Clock for the MMC controller. ICOCZ LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. RTC clock. (output) Real-time clock 1 Hz tick. LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. 3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator. LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. 32 kHz clock. (output) Output from the 32 kHz oscillator. LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. Memory Controller grant. (output) Notifies an external device it has been granted the system bus. LCD frame clock. (output) Indicates the start of a new frame. Also referred to as Vsync. LCD line clock. (output) Indicates the start of a new line. Also referred to as Hsync. LCD pixel clock. (output) Clocks valid pixel data into the LCD line-shift buffer. AC bias drive. (output) Notifies the panel to change the polarity for some passive LCD panel. For TFT panels, this signal indicates valid pixel data. Reset State Pulled High Note[1] Sleep State
ICOCZ
Note [3]
L_DD[10]/ GPIO[68] L_DD[11]/ GPIO[69] L_DD[12]/ GPIO[70] L_DD[13]/ GPIO[71] L_DD[14]/ GPIO[72] L_DD[15]/ GPIO[73] L_FCLK/ GPIO[74] L_LCLK/ GPIO[75] L_PCLK/ GPIO[76] L_BIAS/ GPIO[77]
ICOCZ
Pulled High Note[1]
Note [3]
ICOCZ
Pulled High Note[1] Pulled High Note[1]
Note [3]
Note [3]
ICOCZ
Pulled High Note[1]
Note [3]
ICOCZ
Pulled High Note[1]
Note [3]
ICOCZ
Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1]
Note [3]
ICOCZ ICOCZ ICOCZ
Note [3] Note [3] Note [3]
ICOCZ
Note [3]
Full Function UART Pins FFRXD/ GPIO[34] FFTXD/ GPIO[39] FFCTS/ GPIO[35] FFDCD/ GPIO[36] FFDSR/ GPIO[37] Full function UART receive. (input) ICOCZ MMC chip select 0. (output) Chip select 0 for the MMC Controller. Full Function UART transmit. (output) ICOCZ MMC chip select 1. (output) Chip select 1 for the MMC Controller. Full function UART clear-to-send. (input) Full function UART data-carrier-detect. (input) Full function UART data-set-ready. (input) Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Note [3]
Note [3]
ICOCZ ICOCZ ICOCZ
Note [3] Note [3] Note [3]
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Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
Package Information
Table 3.
Pin Name FFRI/ GPIO[38] FFDTR/ GPIO[40] FFRTS/ GPIO[41]
Pin and Signal Descriptions for the PXA255 Processor (Sheet 5 of 9)
Type ICOCZ ICOCZ ICOCZ Signal Descriptions Full function UART ring indicator. (input) Full function UART data-terminal-ready. (output) Full function UART request-to-send. (output) Reset State Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Sleep State Note [3] Note [3] Note [3]
Bluetooth UART Pins BTRXD/ GPIO[42] BTTXD/ GPIO[43] BTCTS/ GPIO[44] BTRTS/ GPIO[45] ICOCZ ICOCZ ICOCZ ICOCZ Bluetooth UART receive. (input) Bluetooth UART transmit. (output) Bluetooth UART clear-to-send. (input) Bluetooth UART request-to-send. (output) Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Note [3] Note [3] Note [3] Note [3]
Standard UART and ICP Pins IRRXD/ GPIO[46] IRTXD/ GPIO[47] ICOCZ IrDA receive signal. (input) Receive pin for the FIR function. Standard UART receive. (input) ICOCZ IrDA transmit signal. (output) Transmit pin for the Standard UART, SIR and FIR functions. Standard UART transmit. (output) Pulled High Note[1] Pulled High Note[1] Note [3]
Note [3]
Hardware UART Pins HWRXD/ GPIO[42/49] HWTXD/ GPIO[43/48] HWCTS/ GPIO[44/50] HWRTS/ GPIO[45/51] ICOCZ ICOCZ ICOCZ ICOCZ Hardware UART receive. (input) Hardware UART transmit. (output) Hardware UART clear-to-send. (input) Hardware UART data-terminal-ready. (output) Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Note [3] Note [3] Note [3] Note [3]
MMC Controller Pins MMCMD MMDAT nPCE[2]/ GPIO[53] ICOCZ ICOCZ Multimedia card command. (bidirectional) Multimedia card data. (bidirectional) PCMCIA card enable 2. (outputs) Selects a PCMCIA card. Bit one enables the high byte lane and bit zero enables the low byte lane. MMC clock. (output) Clock signal for the MMC controller. L_DD[9]/ GPIO[67] LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. MMC chip select 0. (output) Chip select 0 for the MMC controller. Pulled High Note[1] Hi-Z Hi-Z Pulled High Note[1] Hi-Z Hi-Z
ICOCZ
Note [5]
ICOCZ
Note [3]
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
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Package Information
Table 3.
Pin Name L_DD[10]/ GPIO[68] L_DD[11]/ GPIO[69] FFRXD/ GPIO[34] FFTXD/ GPIO[39] MMCCLK/ GP[6] MMCCS0/ GP[8] MMCCS1/ GP[9] SSP Pins SSPSCLK/ GPIO[23] SSPSFRM/ GPIO[24] SSPTXD/ GPIO[25] SSPRXD/ GPIO[26] SSPEXTCLK/ GPIO[27] NSSP Pins NSSPSCLK/ GPIO[81] NSSPSFRM/ GPIO[82] NSSPTXD/ GPIO[83] NSSPRXD/ GPIO[84] USB Client Pins USB_P USB_N
Pin and Signal Descriptions for the PXA255 Processor (Sheet 6 of 9)
Type Signal Descriptions LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. MMC chip select 1. (output) Chip select 1 for the MMC controller. LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. MMC clock. (output) Clock for the MMC controller. Full function UART receive. (input) ICOCZ MMC chip select 0. (output) Chip select 0 for the MMC controller. Full function UART transmit. (output) ICOCZ MMC chip select 1. (output) Chip select 1 for the MMC controller. MMC clock. (output) Clock signal for the MMC controller. MMC chip select 0. (output) Chip select 0 for the MMC controller. MMC chip select 1. (output) Chip select 1 for the MMC controller. Reset State Pulled High Note[1] Sleep State
ICOCZ
Note [3]
ICOCZ
Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1]
Note [3]
Note [3]
Note [3]
ICOCZ ICOCZ ICOCZ
Note [3] Note [3] Note [3]
ICOCZ ICOCZ ICOCZ ICOCZ ICOCZ
Synchronous serial port clock. (output) Synchronous serial port frame. (output) Synchronous serial port transmit. (output) Synchronous serial port receive. (input) Synchronous serial port external clock. (input)
Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1]
Note [3] Note [3] Note [3] Note [3] Note [3]
ICOCZ ICOCZ ICOCZ ICOCZ
Network synchronous serial port clock. (output/input) Network synchronous serial port frame. (output/input) Network synchronous serial port transmit/recieve. (output/input) Network synchronous serial port transmit/receive. (output/input)
Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1]
Note [3] Note [3] Note [3] Note [3]
IAOAZ IAOAZ
USB client positive. (bidirectional) USB client negative pin. (bidirectional)
Hi-Z Hi-Z
Hi-Z Hi-Z
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Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
Package Information
Table 3.
Pin Name
Pin and Signal Descriptions for the PXA255 Processor (Sheet 7 of 9)
Type Signal Descriptions Reset State Sleep State
AC97 Controller and I2S Controller Pins AC97 audio port bit clock. (input) AC97 clock is generated by Codec 0 and fed into the PXA255 processor processor and Codec 1. BITCLK/ GPIO[28] ICOCZ AC97 Aaudio port bit clock. (output) AC97 clock is generated by the PXA255 processor. I S bit clock. (input) I S clock is generated externally and fed into PXA255 processor. I2S bit clock. (output) I2S clock is generated by the PXA255 processor. SDATA_IN0/ GPIO[29] SDATA_IN1/ GPIO[32] SDATA_OUT/ GPIO[30] SYNC/ GPIO[31] nACRESET
2 2 2
Pulled High Note[1]
Note [3]
ICOCZ
AC97 audio port data in. (input) Input line for Codec 0. I2S data in. (input) Input line for the I2S controller. AC97 audio port data in. (input) Input line for Codec 1. I2S system clock. (output) System clock from I2S controller. AC97 audio port data out. (output) Output from the PXA255 processor to Codecs 0 and 1. I2S data out. (output) Output line for the I 2S controller. AC97 audio port sync signal. (output) Frame sync signal for the AC97 controller. I2S sync. (output) Frame sync signal for the I2S controller. AC97 audio port reset signal. (output)
Pulled High Note[1] Pulled High Note[1] Pulled High Note[1]
Note [3]
ICOCZ
Note [3]
ICOCZ
Note [3]
ICOCZ
Pulled High Note[1] Driven Low
Note [3]
OC
Driven Low
I C Controller Pins SCL SDA PWM Pins PWM[1:0]/ GPIO[17:16] DMA Pins DREQ[1:0]/ GPIO[19:20] GPIO Pins GPIO[1:0] GPIO[14:2] GPIO[22:21] ICOCZ ICOCZ ICOCZ General purpose I/O. Wakeup sources on both rising and falling edges on nRESET. General purpose I/O. More wakeup sources for sleep mode. General purpose I/O. Additional General Purpose I/O pins. Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Note [3] Note [3] Note [3] ICOCZ DMA request. (input) Notifies the DMA Controller that an external device requires a DMA transaction. DREQ[1] is GPIO[19]. DREQ[0] is GPIO[20]. Pulled High Note[1] Note [3] ICOCZ Pulse width modulation channels 0 and 1. (outputs) Pulled High Note[1] Note [3] ICOCZ ICOCZ I2C clock. (bidirectional) I C data. (bidirectional).
2
Hi-Z Hi-Z
Hi-Z Hi-Z
Crystal and Clock Pins PXTAL PEXTAL TXTAL OA IA OA 3.6864 MHz crystal input. No external caps are required. 3.6864 MHz crystal output. No external caps are required. 32 KHz crystal input. No external caps are required. Note [2] Note [2] Note [2] Note [2] Note [2] Note [2]
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
15
Package Information
Table 3.
Pin Name TEXTAL L_DD[12]/ GPIO[70]
Pin and Signal Descriptions for the PXA255 Processor (Sheet 8 of 9)
Type IA ICOCZ Signal Descriptions 32 kHz crystal output. No external caps are required. LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. RTC clock. (output) Real time clock 1 Hz tick. LCD display data. (output) Transfers the pixel information from the LCD controller to the external LCD panel. 3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator. ICOCZ LCD display data. (output) Transfers pixel information from the LCD controller to the external LCD panel. 32 kHz clock. (output) Output from the 32 kHz oscillator. ICOCZ 48 MHz clock. (output) Peripheral clock output derived from the PLL. NOTE: This clock is only generated when the USB unit clock enable is set. Real time clock. (output) 1 Hz output derived from the 32 kHz or 3.6864 MHz output. 3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator. 32 kHz clock. (output) Output from the 32 kHz oscillator. Reset State Note [2] Pulled High Note[1] Sleep State Note [2] Note [3]
L_DD[13]/ GPIO[71]
ICOCZ
Pulled High Note[1]
Note [3]
L_DD[14]/ GPIO[72]
Pulled High Note[1]
Note [3]
48MHz/GP[7] RTCCLK/ GP[10] 3.6MHz/GP[11] 32kHz/GP[12]
Pulled High Note[1] Pulled High Note[1] Pulled High Note[1] Pulled High Note[1]
Note [3]
ICOCZ ICOCZ ICOCZ
Note [3] Note [3] Note [3]
Miscellaneous Pins BOOT_SEL [2:0] IC Boot select pins. (input) Indicates type of boot device. Input Input Driven low while entering sleep mode. Driven high when sleep exit sequence begins.
PWR_EN
OC
Power Enable for the power supply. (output) When negated, it signals the power supply to remove power to the core because the system is entering sleep mode. Main Battery Fault. (input) Signals that main battery is low or removed. Assertion causes PXA255 processor processor to enter sleep mode or force an imprecise data exception, which cannot be masked. PXA255 processor will not recognize a wake-up event while this signal is asserted. Minimum assertion time for nBATT_FAULT is 1 ms. VDD Fault. (input) Signals that the main power source is going out of regulation. nVDD_FAULT causes the PXA255 processor to enter sleep mode or force an imprecise data exception, which cannot be masked. nVDD_FAULT is ignored after a wake-up event until the power supply timer completes (approximately 10 ms). Minimum assertion time for nVDD_FAULT is 1 ms. Hard reset. (input) Level -sensitive input used to start the processor from a known address. Assertion terminates the current instruction abnormally and causes a reset. When nRESET is driven high, the processor starts execution from address 0. nRESET must remain low until the power supply is stable and the internal 3.6864 MHz oscillator has stabilized.
Driven High
nBATT_FAULT
IC
Input
Input
nVDD_FAULT
IC
Input
Input
nRESET
IC
Input
Input. Driving low during sleep will cause normal reset sequence and exit from sleep mode.
16
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
Package Information
Table 3.
Pin Name
Pin and Signal Descriptions for the PXA255 Processor (Sheet 9 of 9)
Type Signal Descriptions Reset out. (output) Asserted when nRESET is asserted and deasserts after nRESET is de-asserted but before the first instruction fetch. nRESET_OUT is also asserted for "soft" reset events: sleep, watchdog reset, or GPIO reset. Reset State Driven low during any reset sequence - driven high prior to first fetch. Sleep State
nRESET_OUT
OC
Driven Low
JTAG and Test Pins JTAG test interface reset. Resets the JTAG/debug port. If JTAG/debug is used, drive nTRST from low to high either before or at the same time as nRESET. If JTAG is not used, nTRST must be either tied to nRESET or tied low. JTAG test data input. (input) Data from the JTAG controller is sent to the PXA255 processor using this pin. This pin has an internal pull-up resistor. JTAG test data output. (output) Data from the PXA255 processor is returned to the JTAG controller using this pin. JTAG test mode select. (input) Selects the test mode required from the JTAG controller. This pin has an internal pull-up resistor. JTAG test clock. (input) Clock for all transfers on the JTAG test interface. Test Mode. (input) Reserved. Must be grounded. Test Clock. (input) Reserved. Must be grounded.
nTRST
IC
Input
Input
TDI
IC
Input
Input
TDO
OCZ
Hi-Z
Hi-Z
TMS TCK TEST TESTCLK
IC IC IC IC
Input Input Input Input
Input Input Input Input
Power and Ground Pins VCC VSS PLL_VCC PLL_VSS VCCQ SUP SUP SUP SUP SUP Positive supply for internal logic. Must be connected to the low voltage supply on the PCB. Ground supply for internal logic. Must be connected to the common ground plane on the PCB. Positive supply for PLLs and oscillators. Must be connected to the common low voltage supply. Ground supply for the PLL. Must be connected to common ground plane on the PCB. Positive supply for all CMOS I/O except memory bus and PCMCIA pins. Must be connected to the common 3.3v supply on the PCB. Ground supply for all CMOS I/O except memory bus and PCMCIA pins. Must be connected to the common ground plane on the PCB. Positive supply for memory bus and PCMCIA pins. Must be connected to the common 3.3v or 2.5v supply on the PCB. Ground supply for memory bus and PCMCIA pins. Must be connected to the common ground plane on the PCB. Powered Grounded Powered Grounded Powered Note [6] Grounded Note [6] Grounded Note [7]
VSSQ
SUP
Grounded
Grounded
VCCN
SUP
Powered
Note [7]
VSSN
SUP
Grounded
Grounded
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
17
Package Information
Table 4.
Note
Pin Description Notes
Description GPIO reset operation: Configured as GPIO inputs by default after any reset. The input buffers for these pins are disabled to prevent current drain and the pins are pulled high with 10K to 60K internal resistors. The input paths must be enabled and the pullups turned off by clearing the read-disable-hold (RDH) bit described in Section 3.5.7, "Power Manager Sleep Status Register (PSSR)" on page 3-27 in the Intel(R) PXA255 Processor Developers Manual. Even though sleep mode sets the RDH bit, the pull-up resistors are not re-enabled by sleep mode. Crystal oscillator pins: These pins connect the external crystals to the on-chip oscillators. Refer to Section 3.3.1, "32.768 kHz Oscillator" on page 3-4 in the Intel(R) PXA255 Processor Developers Manual and Section 3.3.2, "3.6864 MHz Oscillator" on page 3-4 of the Intel(R) PXA255 Processor Developers Manual for details on sleepmode operation. GPIO sleep operation: The state of these pins is determined by the corresponding PGSRn during the transition into sleep mode. See Section 3.5.9, "Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2)" and Section 4.1.3.2, "GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)" on page 4-8 in the Intel(R) PXA255 Processor Developers Manual. If selected as an input, this pin does not drive during sleep. If selected as an output, the value contained in the sleep-state register is driven out onto the pin and held there while the PXA255 processor is in sleep mode. GPIOs configured as inputs after exiting sleep mode cannot be used until PSSR[RDH] is cleared. Static memory control pins: During sleep mode, these pins can be programmed to either drive the value in the sleep-state register or be placed in Hi-Z. To select the Hi-Z state, software must set the FS bit in the powermanager general-configuration register. If PCFR[FS] is not set, then during the transition to sleep these pins function as described in [3], above. For nWE, nOE, and nCS[0], if PCFR[FS] is not set, they are driven high by the memory controller before entering sleep. If PCFR[FS] is set, these pins are placed in Hi-Z. PCMCIA control pins: During sleep mode: can be programmed either to drive the value in the sleep-state register or be placed in Hi-Z. To select the Hi-Z state, software must set PCFR[FP]. If it is not set, then during the transition to sleep these pins function as described in [3], above. During sleep, this supply may be driven low. This supply must never be high impedance. Remains powered in sleep mode.
[1]
[2]
[3]
[4]
[5] [6] [7]
18
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
Package Information
Figure 2. PXA255 processor
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
19
Package Information
Table 5.
PXA255 processor 256-Lead 17x17mm mBGA Pinout -- Ballpad No. Order (Sheet 1 of 3)
Ball # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 VCCN L_DD[13]/GPIO[71] L_DD[12]/GPIO[70] L_DD[11]/GPIO[69] L_DD[9]/GPIO[67] L_DD[7]/GPIO[65] GPIO[11] L_BIAS/GPIO[77] SSPRXD/GPIO[26] SDATA_OUT/GPIO[30] SDA FFDCD/GPIO[36] FFRXD/GPIO[34] FFCTS/GPIO[35] BTCTS/GPIO[44] SDATA_IN1/GPIO[32] DQM[1] DQM[2] L_DD[15]/GPIO[73] GPIO[14] GPIO[13] GPIO[12] L_DD[3]/GPIO[61] L_PCLK/GPIO[76] SSPEXTCLK/GPIO[27] FFRI/GPIO[38] FFDSR/GPIO[37] USB_N BTRXD/GPIO[42] BTRTS/GPIO[45] IRRXD/GPIO[46] MMDAT RDY/GPIO[18] VSSN L_DD[14]/GPIO[72] VSSQ Signal Ball # C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 VCCQ VSSQ USB_P VCCQ VSSQ IRTXD/GPIO[47] VSS SDCLK[2] SDCLK[0] RDnWR VCCN L_DD[10]/GPIO[68] L_DD[5]/GPIO[63] L_DD[1]/GPIO[59] L_LCLK/GPIO[75] SSPTXD/GPIO[25] nACRESET SCL PWM[1]/GPIO[17] BTTXD/GPIO[43] MMCMD VCCQ NSSPRXD/GPIO[84] nSDRAS VSSN SDCKE[1] SDCKE[0] L_DD[6]/GPIO[64] L_DD[4]/GPIO[62] L_DD[[0]/GPIO[58] L_FCLK/GPIO[74] SSPSFRM/GPIO[24] SDATA_IN0/GPIO[29] SYNC/GPIO[31] PWM[0]/GPIO[16] FFTXD/GPIO[39] Signal Ball # F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 nSDCAS VCCN SDCLK[1] VSSQ GPIO[10] FFRTS/GPIO[41] SSPSCLK/GPIO[23] FFDTR/GPIO[40] VCC GPIO[9] BOOT_SEL[2] GPIO[8] VSSQ NSSPSCLK/GPIO[81] MA[0] VSSN nSDCS[2] nWE nOE nSDCS[1] VCC VSSQ VCC VSSQ TESTCLK TEST BOOT_SEL[1] VCCQ GPIO[7] BOOT_SEL[0] MA[2] MA[1] MD[16] VCCN MD[17] MA[3] Signal
20
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
Package Information
Table 5.
PXA255 processor 256-Lead 17x17mm mBGA Pinout -- Ballpad No. Order (Sheet 2 of 3)
Ball # C5 C6 C7 C8 C9 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 Signal L_DD[8]/GPIO[66] VCCQ L_DD[2]/GPIO[60] VSSQ BITCLK/GPIO[28] TCK TMS GPIO[6] TDI TDO MA[7] VSSN MA[6] MD[18] MA[5] MA[4] VCC VSS VSS VSSQ GPIO[5] GPIO[4] nRESET VSSQ PLL_VCC PLL_VSS MA[8] MA[9] MD[19] VCCN MA[10] MA[11] VSSQ VCC VSSQ VCC nRESET_OUT Ball # E14 E15 E16 F1 F2 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 VCCQ NSSPTXD/GPIO[83] NSSPSFRM/GPIO[82] nSDCS[0] nSDCS[3] VCC GPIO[0] PWR_EN GPIO[1] GPIO[2] VSSQ TEXTAL TXTAL MA[14] MD[21] MA[15] VCCN MD[1] MD[6] MD[7] DQM[0] MD[8] MD[15] VCCQ GPIO[22] nPREG/GPIO[55] VCCN VSSN nIOIS16/GPIO[57] MD[22] VSSN MA[16] MD[0] VCCN MD[4] VCCN nCS[0] Signal Ball # H7 H8 H9 H10 H11 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 VSSQ VSS VSS VCC nTRST MD[24] MD[26] MD[27] nCS[2]/GPIO[78] MD[29] MD[12] MD[31] nPOE/GPIO[48] nPCE[1]/GPIO[52] VSSN nPSKTSEL/GPIO[54] MA[18] VSSN MA[20] VSSN MA[22] VSSN MD[25] VSSN MD[10] VSSN MD[30] VSSN nCS[4]/GPIO[80] VSSN nPIOW/GPIO[51] nPCE[2]/GPIO[53] VSS VCCN MD[23] MA[21] MA[24] Signal
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
21
Electrical Specifications
Table 5.
PXA255 processor 256-Lead 17x17mm mBGA Pinout -- Ballpad No. Order (Sheet 3 of 3)
Ball # K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 Signal nBATT_FAULT nVDD_FAULT GPIO[3] PXTAL PEXTAL MA[12] VSSN MA[13] MD[20] MD[2] VCC DQM[3] MD[28] Ball # N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 VCCN MD[13] VCCN DREQ[0]/GPIO[20] VCCN DREQ[1]/GPIO[19] GPIO[21] nPWAIT/GPIO[56] MA[17] MA[19] VCCN MA[25] MA[23] Signal Ball # T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 MD[3] MD[5] nCS[1]/GPIO[15] nCS[3]/GPIO[79] MD[9] MD[11] MD[14] nCS[5]/GPIO[33] nPWE/GPIO[49] nPIOR/GPIO[50] VCCN Signal
3.2
Table 6.
Package Power Ratings
JA and Maximum Power Ratings
Processor PXA255
JA
33 C/w
Max Power 1.4W
4.0
4.1
Electrical Specifications
Absolute Maximum Ratings
This section provides the absolute maximum ratings for the processors. Do not exceed these parameters or the part may be damaged permanently. Operation at absolute maximum ratings is not guaranteed.
22
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
Electrical Specifications
Table 7.
Absolute Maximum Ratings
Symbol TS VSS_O VCC_O VCC_HV VCC_LV VIP Storage Temperature Offset Voltage between any two VSS pins (VSS, VSSQ, VSSN) Offset Voltage between any of the following pins: VCCQ and VCCN Voltage Applied to High Voltage Supplies (VCCQ, VCCN) Voltage Applied to Low Voltage Supplies (VCC, PLL_VCC) Voltage Applied to non-Supply pins except XTAL pins Voltage Applied to XTAL pins (PXTAL, PEXTAL, TXTAL, TEXTAL) Maximum ESD stress voltage, Human Body Model; Any pin to any supply pin, either polarity, or Any pin to all nonsupply pins together, either polarity. Three stresses maximum. Maximum DC Input Current (Electrical Overstress) for any non-supply pin Description Min -40 -0.3 -0.3 VSS-0.3 VSS-0.3 VSS-0.3 Max 125 0.3 0.3 VSS+4.0 VSS+1.65 max of VCCQ+0.3, VSS+4.0 max of VCC+0.3, VSS+1.65 2000 Units C V V V V V
VIP_X
VSS-0.3
V
VESD
V
IEOS
5
mA
4.2
Power Consumption Specifications
Power consumption depends on the operating voltage, peripherals enabled, external switching activity, and external loading. Specifying maximum power consumption requires all units to be run at their maximum performance, and at maximum voltage and loading conditions. The maximum power consumption of the PXA255 processor is calculated using these conditions:
* * * *
All peripheral units operating at maximum frequency and size configuration All I/O loads maximum (50 pF) Core operating at worst-case power scenario (hit rates adjusted for worst power) All voltages at maximum of range. Maximum range for the core voltage is set to maintain compatibility with the PXA250.
* Maximum case temperature
Do not exceed the maximum package power rating or Tcase temperature. Since few systems operate at maximum loading, performance, and voltage, a more optimal system design requires more typical power-consumption figures. These figures are important when considering battery size and optimizing regulator efficiency. Typical systems operate with fewer modules active and at nominal voltage and load. The typical power consumption for the PXA255 processor is calculated using these conditions:
* SSP, STUART, USB, PWM, Timer, I2S peripherals operating
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
23
Electrical Specifications
* * * * * *
LCD enabled with 320x240x16-bit color MMC, AC97, BTUART, FFUART, ICP, I2C peripherals disabled I/O loads at nominal (35 pf for all pins) Core operating at 98% instruction hit rate, 95% data hit rate, run mode All voltages at nominal values Nominal case temperature
Table 8 contains power consumption numbers for the PXA255 processor. Table 8. Power Consumption Specifications for PXA255 processor (Sheet 1 of 2)
Symbol Description Typical Maximum Units
400 MHz active mode, Maximum: V cc=1.65V, Vccq/Vccn=3.6V, Temp=100 C Typical: Vcc=1.3V, Vccq/Vccn=3.3V, Temp=Room Iccc Iccp PTOTAL Vcc Current Vccq and Vccn Current Total Power 245 28 411 800 355 2598 mA mA mW
300 MHz active mode, Maximum: V cc=1.43V, Vccq/Vccn=3.6V, Temp=100 C Typical: Vcc=1.1V, Vccq/Vccn=3.3V, Temp=Room Iccc Iccp PTOTAL Vcc Current Vccq and Vccn Current Total Power 185 24 283 570 345 2057 mA mA mW
200 MHz active mode, Maximum: V cc=1.32V, Vccq/Vccn=3.6V, Temp=100 C Typical: Vcc=1.0V, Vccq/Vccn=3.3V, Temp=Room Iccc Iccp PTOTAL Vcc Current Vccq and Vccn Current Total Power 115 19 178 340 330 1637 mA mA mW
400 MHz idle mode, Maximum: Vcc =1.65V, Vccq/Vccn=3.6V, Temp=100 C Typical: Vcc=1.3V, Vccq/Vccn=3.3V, Temp=Room Iccc Iccp PTOTAL Vcc Current Vccq and Vccn Current Total Power 95 9 121 460 50 939 mA mA mW
300 MHz idle mode, Maximum: Vcc =1.43V, Vccq/Vccn=3.6V, Temp=100 C Typical: Vcc=1.1V, Vccq/Vccn=3.3V, Temp=Room Iccc Iccp PTOTAL Vcc Current Vccq and Vccn Current Total Power 43 9 77 335 50 659 mA mA mW
200 MHz idle mode, Maximum: Vcc =1.32V, Vccq/Vccn=3.6V, Temp=100 C Typical: Vcc=1.0V, Vccq/Vccn=3.3V, Temp=Room Iccc Iccp PTOTAL Vcc Current Vccq and Vccn Current Total Power 33 9 63 205 50 451 mA mA mW
33 MHz idle mode, Maximum: Vcc =1.32V, Vccq/Vccn=3.6V, Temp=100 C Typical: Vcc=1.0V, Vccq/Vccn=3.3V, Temp=Room
24
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
Electrical Specifications
Table 8.
Power Consumption Specifications for PXA255 processor (Sheet 2 of 2)
Symbol Iccc Iccp PTOTAL Iccp Iccc Iccp Description Vcc Current Vccq and Vccn Current Total Power Typical 15 9 45 Maximum 70 50 272 Units mA mA mW
Sleep mode, Maximum: Vcc=0V, Vccq/Vccn=3.3V, Temp=Room Vccq and Vccn Current Vcc Current Vccq and Vccn Current 45 75 A - Fast sleep wakeup mode, Maximum: V cc =1.0/1.1/1.3V, Vccq/Vccn=3.3V, Temp=Room -
4.3
Operating Conditions
This section shows voltage, frequency, and temperature specifications for the processor for four different ranges (shown in Table 9, "Voltage, Temperature, and Frequency Electrical Specifications".) The temperature specification for each range is constant; the frequency range depends on the operation voltage. Note: The parameters in Table 9 are preliminary and subject to change. Voltage, Temperature, and Frequency Electrical Specifications (Sheet 1 of 2)
Symbol Tcase Tcase VVSS VVCCQ VVCCN Description Case Temperature - Extended Temp Case Temperature - Nominal Temp VSS, VSSN, VSSQ Voltage VCCQ Voltage VCCN Voltage Min -40 0 -0.3 3.0 2.375 Typical 0 3.3 2.5/3.3 Max 100 85 0.3 3.6 3.6 Units C C V V V
Table 9.
Low Voltage Range VVCC_L fTURBO_L fSDRAM_L VCC, PLL_VCC Voltage, Low Range Turbo Mode Frequency, Low Range External Synchronous Memory Frequency, Low Range .95 99.5 50 1.00 1.155 118 99.5 V MHz MHz
Medium Voltage Range VVCC_M fTURBO_M fSDRAM_M VCC, PLL_VCC Voltage, Mid Range Turbo Mode Frequency, Mid Range External Synchronous Memory Frequency, Mid Range .95 99.5 50 1.00 1.32 199.1 99.5 V MHz MHz
High Voltage Range VVCC_H fTURBO_H fSDRAM_H VCC, PLL_VCC Voltage, High Range Turbo Mode Frequency, High Range External Synchronous Memory Frequency, High Range 1.045 99.5 50 1.1 1.43 298.7 99.5 V MHz MHz
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
25
Electrical Specifications
Table 9.
Voltage, Temperature, and Frequency Electrical Specifications (Sheet 2 of 2)
Symbol Peak Voltage Range VVCC_P fTURBO_P fSDRAM_P VCC, PLL_VCC Voltage, Peak Range Turbo Mode Frequency, Peak Range External Synchronous Memory Frequency, Peak Range 1.235 99.5 50 1.30 1.65 398.2 99.5 V MHz MHz Description Min Typical Max Units
4.4
Targeted DC Specifications
The DC characteristics for each pin include input-sense levels and output-drive levels and currents. These parameters can be used to determine maximum DC loading, and also to determine maximum transition times for a given load. Table 10, "Standard Input, Output, and I/O Pin DC Operating Conditions" shows the DC operating conditions for the high- and low-strength input, output, and I/O pins. All DC specification values are valid for the entire temperature range of the device.
Table 10. Standard Input, Output, and I/O Pin DC Operating Conditions
Symbol Input DC Operating Conditions VIH VIL IIN Input High Voltage, all standard input and I/O pins Input Low Voltage, all standard input and I/O pins Input Leakage, all standard input and IO pins 0.8*VCCQ VSS VCCQ 0.2*VCCQ 10 V V A Description Min Typical Max Units
Output DC Operating Conditions VOH VOL IOH_H IOH_L IOL_H IOL_L Output High Voltage, all standard output and I/O pins Output Low Voltage, all standard output and I/O pins Output High Current, all standard, highstrength output and I/O pins (VO=VOH) Output High Current, all standard, lowstrength output and I/O pins (VO=VOH) Output Low Current, all standard, highstrength output and I/O pins (VO=VOH) Output Low Current, all standard, lowstrength output and I/O pins (VO=VOH) VCCQ-0.1 VSS -10 -3 10 3 VCCQ VSS+0.4 V V mA mA mA mA
26
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
Electrical Specifications
Table 11. Standard Input, Output, I/O Pin DC Operating Conditions for 2.5-V Memory
Symbol Description Min Typ Max Units
Input DC Operating Conditions Vih Vil Iin Input High Voltage, all standard input and I/O pins Input Low Voltage, all standard input and I/O pins Input Leakage, all standard input and I/O pins 0.9*VCCN VSS VCCN 0.1*VCCN 10 V V uA
Output DC Operating Conditions Voh Vol Output High Voltage, all standard output and I/O pins Output Low Voltage, all standard output and I/O pins VCCN-0.3 VSS VCCN VSS+0.3 V V
4.5
Targeted AC Specifications
All the non-analog input, output, and I/O pins on the processor can be divided into one of two categories: 1. High Strength Input, Output, and I/O pins:
* * * * * * * * * *
nCS[5:1] (GP 33, 80, 79, 78, 15 respectively), nCS[0] MD[31:0], MA[25:0] DQM[3:0] nOE, nWE, nSDRAS, nSDCAS, nSDCS[3:0] SDCLK[2:0], SDCKE[1:0] RDnWR, RDY (GP[18]) nPWE, nPOE pins (GP[49:48]) MMCLK (GP[53]), MMCMD, MMDAT TDO nACRESET
2. Low Strength Input, Output, and I/O pins - all remaining non-supply pins A pin's AC characteristics include input and output capacitance, which determine loading for external drivers or other load analysis. The AC characteristics also include a de-rating factor, which indicates how much faster or slower the AC timings get with different loads. Table 12, "Standard Input, Output, and I/O Pin AC Operating Conditions" shows the AC operating conditions for the high- and low-strength input, output, and I/O pins. All AC specification values are valid for the entire temperature range of the device.
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
27
Electrical Specifications
Table 12. Standard Input, Output, and I/O Pin AC Operating Conditions
Symbol CIN COUT_H tdF_H Description Input capacitance, all standard input and IO pins Output capacitance, all standard highstrength output and IO pins Output de-rating, falling edge on all standard, high-strength output and I/O pins, from 50pF load. Output de-rating, rising edge on all standard, high-strength output and I/O pins, from 50pF load. 251 Min Typical Max 10 501 Units pF pF ns/pF
tdR_H NOTE:
1
ns/pF
AC specifications guaranteed for loads in this range. All testing is done at 50pF
4.6
Oscillator Electrical Specifications
The processor contains two oscillators, each for a specific crystal: a 32.768-kHz oscillator and a 3.6864-MHz oscillator. When choosing a crystal, match the crystal parameters as closely as possible.
4.6.1
32.768-kHz Oscillator Specifications
The 32.768-kHz oscillator is connected between the TXTAL (amplifier input) and TEXTAL (amplified output). Table 13, "32.768-kHz Oscillator Specifications" shows the 32.768-kHz specifications.
Table 13. 32.768-kHz Oscillator Specifications
Symbol Description Min Typical Max Units
Crystal Specifications - Typical is FOX NC38 FXT ESR P Crystal Frequency, TXTAL/TEXTAL Equivalent series resistance, TXTAL/TEXTAL Drive Level -- 6 -- 32.768 -- -- -- 65 1 kHz k uW
Amplifier Specifications VIH_X VIL_X IIN_XT CIN_XT tS_XT Input High Voltage, TXTAL Input Low Voltage, TXTAL Input Leakage, TXTAL Input Capacitance, TXTAL/TEXTAL Stabilization Time 2 18 0.8*VCC VSS VCC 0.2*VCC 1 25 10 V V A pF s
Board Specifications RP_XT CP_XT COP_XT Parasitic Resistance, TXTAL/TEXTAL to any node Parasitic Capacitance, TXTAL/TEXTAL, total Parasitic Shunt Capacitance, TXTAL to TEXTAL 20 5 0.4 M pF pF
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To drive the 32.768-kHz crystal pins from an external source
* Drive the TEXTAL pin with a digital signal that has a low level near 0 volts and a high level
near VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is 1 volt per 1 s. The maximum current sourced by the external clock source when the clock is at its maximum positive voltage should be approximately 1 mA. level, slew rate, and input current restrictions.
* Float the TXTAL pin or drive it complementary to the TEXTAL pin, with the same voltage 4.6.2 3.6864 MHz Oscillator Specifications
The 3.6864-MHz oscillator is connected between the PXTAL (amplifier input) and PEXTAL (amplified output). Table 14 shows the 3.6864-MHz specifications. Table 14. 3.6864-MHz Oscillator Specifications
Symbol Description Min Typical Max Units
Crystal Specifications - Typical is FOX HC49S FXP ESR P Crystal Frequency, PXTAL/PEXTAL Equivalent series resistance, PXTAL/PEXTAL Drive Level -- 50 -- 3.6864 -- -- 300 100 MHz uW
Amplifier Specifications VIH_X VIL_X IIN_XP CIN_XP tS_XP Input High Voltage, PXTAL Input Low Voltage, PXTAL Input Leakage, PXTAL Input Capacitance, PXTAL/PEXTAL Stabilization Time 17.8 40 0.8*VCC VSS VCC 0.2*VCC 10 50 67.8 V V A pF ms
Board Specifications RP_XP CP_XP COP_XP Parasitic Resistance, PXTAL/PEXTAL to any node Parasitic Capacitance, PXTAL/PEXTAL, total Parasitic Shunt Capacitance, PXTAL to PEXTAL 20 5 0.4 M pF pF
To drive the 3.6864-MHz crystal pins from an external source
* Drive the PEXTAL pin with a digital signal with a low level near 0 volts and a high level near
VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is 1 volt / 100 ns. The maximum current sourced by the external clock source when the clock is at its maximum positive voltage should be approximately 1 mA. level, slew rate, and input current restrictions. If floated, some degree of noise susceptibility will be introduced in the system; therefore, it is not recommended.
* Float the PXTAL pin or drive it complementary to the PXTAL pin, with the same voltage
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Electrical Specifications
Note:
The minimum duty cycle for an external signal driven into PEXTAL is 40/60.
4.7
Reset and Power AC Timing Specifications
The processor asserts the nRESET_OUT pin in one of several different modes:
* * * * *
Power on Hardware reset Watchdog reset GPIO reset Sleep mode
The following sections provide the timing and specifications for the entry and exit of these modes.
4.7.1
Power-On Timing
The external voltage regulator and other power-on devices must provide the processor with a specific sequence of power and resets to ensure proper operation. Figure 3, "Power-On Reset Timing" on page 31, shows this sequence and is detailed in Table 15, "Power-On Timing Specifications" on page 31. On the processor, it is important that the power supplies be powered up in a certain order to avoid high current situations. The required order is: 1. VCCQ 2. VCCN 3. VCC and PLL_VCC On the processor, it is important that the VCCQ power supply be powered up before or at the same time as the VCCN power supply. The VCC and PLL_VCC power supplies may be powered up anytime within the specification shown in Figure 3 and Table 15.
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Note:
If hardware reset is entered during sleep mode, follow the proper power-supply stabilization times indicated in Figure 3 and nRESET timing requirements indicated in Table 15.
Figure 3. Power-On Reset Timing
tR_VCCQ
VCCQ, PWR_EN VCCN VCC
tR_VCCN tD_VCCN tR_VCC tD_VCC tD_NTRST
nTRST JTAG PINS nRESET nRESET_OUT
tD_JTAG tD_NRESET tD_OUT
NOTES: 1. nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is deasserted or the processor enters sleep mode. 2. The inclusion of PWR_EN is for informational purposes only to show its relationship to VCCQ. The use of PWR_EN to bring up VCCN or VCC at power-on reset is optional depending on the system's power management requirements. VCCN and VCC are not dependant on the PWR_EN signal being asserted.
Table 15. Power-On Timing Specifications
Symbol tR_VCCQ tR_VCCN tR_VCC tD_VCCN tD_VCC tD_NTRST tD_JTAG tD_NRESET tD_OUT tD_NCS0 Description VCCQ rise / stabilization time VCCN rise / stabilization time VCC, PLL_VCC rise / stabilization time Delay between VCCQ applied and VCCN applied Delay from VCCN applied and VCC, PLL_VCC applied Delay between VCC, PLL_VCC stable and nTRST de-asserted Delay between nTRST de-asserted and JTAG pins active, with nRESET asserted Delay between VCC, PLL_VCC stable and nRESET de-asserted Delay between nRESET de-asserted and nRESET_OUT de--asserted Delay between nRESET_OUT deasserted and nCS0 asserted Min 0.01 0.01 0.01 0 -10 10 0.03 10 18.1 400 Typical -- -- -- -- -- -- -- -- -- -- Max 100 100 10 -- -- -- -- -- 18.2 420 Units ms ms ms ms ms ms ms ms ms ns
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4.7.2
Hardware Reset Timing
The timing sequences shown in hardware reset timing for hardware reset assumes stable power supplies at the assertion of nRESET. If the power supplies are unstable, follow the timings indicated in Section 4.7.1, "Power-On Timing" on page 30.
Figure 4. Hardware Reset Timing
nRESET nRESET_OUT
tDHW_OUT_A
tDHW_NRESET tDHW_OUT Note: nBA TT_FAULT and nVDD_F AULT must be high before Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted is or the Cotulla the enter Sleep Mode de-asserted or will PXA255 processor enters sleep mode.
Table 16. Hardware Reset Timing Specifications
Symbol tDHW_NRESET tDHW_OUT_A tDHW_OUT tDHW_NCS0 Description Minimum assertion time of nRESET Delay between nRESET asserted and nRESET_OUT asserted Delay between nRESET de-asserted and nRESET_OUT de-asserted Delay between nReset_Out de-asserted and nCS0 asserted Min 0.001 0 18.1 400 -- 0.001 18.2 420 Typical Max Units ms ms ms ns
4.7.3
Watchdog Reset Timing
Watchdog reset is an internally generated reset and therefore has no external pin dependencies. The nRESET_OUT pin is the only indicator of watchdog reset, and it stays asserted for tDHW_OUT. Refer to Figure 4, "Hardware Reset Timing" on page 32.
4.7.4
GPIO Reset Timing
GPIO reset is generated externally, and the source is reconfigured as a standard GPIO as soon as the reset propagates internally. The clocks module is not reset by GPIO reset, so the timing varies based on the frequency of clock selected, and if the clocks and power manager is in the frequency change sequence when GPIO reset is asserted (see Section 4.6.1, "32.768-kHz Oscillator Specifications" on page 28.) Figure 5, "GPIO Reset Timing" on page 33 shows the possible timing of GPIO reset.
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Figure 5. GPIO Reset Timing
t GP[1] nRESET_OUT t
A_GP[1]
t
DHW_OUT_A
DHW_OUT
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted or the application processor will enter Sleep Mode
Table 17. GPIO Reset Timing Specifications
Symbol tA_GP[1] tDHW_OUT_A Description Minimum assert time of GP[1] in 3.6864MHz input clock cycles Delay between GP[1] asserted and nRESET_OUT asserted in 3.6864 MHz input clock cycles Delay between nRESET_OUT asserted and nRESET_OUT de-asserted, run or turbo mode2 Delay between nRESET_OUT asserted and nRESET_OUT de-asserted, during frequency change sequence3 Delay between nReset_Out de-asserted and nCS0 asserted
1
Min 4 3
Typical
Max
Units cycles
8
cycles
tDHW_OUT
1.28
6.5
s
tDHW_OUT_F tDHW_NCS0
1.28 150.69 --
360 390
s ns
NOTES: 1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should check the state of GP[1] before configuring as a reset to ensure no spurious reset is generated. 2. Time is 512*N processor clock cycles plus up to 4 cycles of the 3.6864-MHz input clock. 3. Time during the frequency change sequence depends on the state of the PLL lock detector at the assertion of GPIO reset. The lock detector has a maximum time of 350s plus synchronization.
4.7.5
Sleep Mode Timing
Sleep mode is asserted internally; and asserts the nRESET_OUT and PWR_EN signals. The sequence indicated in Figure 6, "Sleep Mode Timing" on page 34 and detailed in Figure 18, "Sleep Mode Timing Specifications" on page 34 is the required timing parameters for sleep mode.
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Electrical Specifications
Figure 6. Sleep Mode Timing
tA_GP[x]
GP[x] PWR_EN VCC nVDD_FAULT nRESET_OUT
Note: nBA TT_FAULT must be high or the PXA255 processor Note: nBATT_FAULT must be high or Cotulla will not exit Sleep Mode will not exit sleep mode. tD_F
A UL T
tD_PWR_F
tD_PWR_R
tDSM_VCC
t
DSM_OUT
Table 18. Sleep Mode Timing Specifications
Symbol tA_GP[x} tD_PWR_F tD_PWR_R tDSM_VCC tD_FAULT tDSM_OUT tDSM_OUT_F tDSM_OUT_O tDSM_NCS0 Description Assert time of GPIO wake-up source (x=[15:0]) Delay from nRESET_OUT asserted to PWR_EN de-asserted Delay between GP[x] asserted to PWR_EN asserted Delay between PWR_EN asserted and VCC stable Delay between PWR_EN asserted and nVDD_FAULT de-asserted Delay between PWR_EN asserted and nRESET_OUT de-asserted, OPDE set Delay between PWR_EN asserted and nRESET_OUT de-asserted, FWAKE set Delay between PWR_EN asserted and nRESET_OUT de-asserted, OPDE clear Delay between nReset_Out de-asserted and nCS0 asserted 28.0 -- 10.35 180.84 Min 91.6 61 30.5 Typical -- -- -- -- -- -- -- -- -- Max -- 91.6 122.1 10 10 28.5 650 10.5 332 Units s s s ms ms ms s ms ns
NOTE: For the parameter tDSM_VCC, VCC refers to the VCC supply internal to the processor. The internal VCC regulator must be stable within the stated maximum for the processor to function correctly. Factors such as external voltage regulator ramp time and bulk capacitance will affect the ramp time of the internal regulator and must be taken into account when designing the system.
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Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
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4.8
Memory Bus and PCMCIA AC Specifications
This section provides the timing information for these types of memory:
* SRAM / ROM / Flash / Synchronous Fast Flash Asynchronous writes (Table 19, "SRAM /
ROM / Flash / Synchronous Fast Flash AC Specifications" on page 35) page 35)
* Variable latency I/O (Table 20, "Variable Latency I/O Interface AC Specifications" on * Card interface (PCMCIA or Compact Flash) (Table 21, "Card Interface (PCMCIA or Compact
Flash) AC Specifications" on page 36) page 36)
* Synchronous memories (Table 22, "Synchronous Memory Interface AC Specifications 1" on
Table 19. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications
Symbol tromAS tromAH tromASW tromAHW tromCES tromCEH tromDS tromDSWH tromDH tromNWE Description MA(25:0) setup to nCS, nOE, nSDCAS (as nADV) asserted MA(25:0) hold after nCS, nOE, nSDCAS (as nADV) deasserted MA(25:0) setup to nWE asserted MA(25:0) hold after nWE de-asserted nCS setup to nWE asserted nCS hold after nWE de-asserted MD(31:0), DQM(3:0) write data setup to nWE asserted MD(31:0), DQM(3:0) write data setup to nWE de-asserted MD(31:0), DQM(3:0) write data hold after nWE de-asserted nWE high time between beats of write data MEMCLKs 1 1 3 1 2 1 1 2 1 2
Table 20. Variable Latency I/O Interface AC Specifications
Symbol tvlioAS tvlioASRW tvlioAH tvlioCES tvlioCEH tvlioDSW tvlioDSWH tvlioDHW tvlioDHR tvlioRDYH tvlioNPWE Description MA(25:0) setubp to nCS asserted MA(25:0) setup to nOE or nPWE asserted MA(25:0) hold after nOE or nPWE de-asserted nCS setup to nOE or nPWE asserted nCS hold after nOE or nPWE de-asserted MD(31:0), DQM(3:0) write data setup to nPWE asserted MD(31:0), DQM(3:0) write data setup to nPWE deasserted MD(31:0), DQM(3:0) hold after nPWE de-asserted MD(31:0) read data hold after nOE de-asserted RDY hold after nOE, nPWE de-asserted nPWE, nOE high time between beats of write or read data MEMCLKs 1 1 1 2 1 1 2 1 0 0 2
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Table 21. Card Interface (PCMCIA or Compact Flash) AC Specifications
Symbol tcardAS tcardAH tcardDS tcardDH tcardCMD Description MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE, nPOE, nPIOW, or nPIOR asserted MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE, nPOE, nPIOW, or nPIOR de-asserted MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR asserted MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR de-asserted nPWE, nPOE, nPIOW, or nPIOR command assertion MEMCLKs 2 2 2 2 2
NOTE: These numbers are minimums. They can be much longer based on the programmable card interface timing registers.
Table 22. Synchronous Memory Interface AC Specifications 1
Symbol Description MIN MAX Units, Notes
SDRAM / SMROM / SDRAM-Timing Synchronous Flash (Synchronous) tsynCLK tsynCMD tsynRCD tsynCAS tsynSDOS SDCLK period nSDCAS, nSDRAS, nWE, nSDCS assert time nSDRAS to nSDCAS assert time nSDCAS to nSDCAS assert time MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE, SDCKE(1:0), RDnWR output setup time to SDCLK(2:0) rise MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE, SDCKE(1:0), RDnWR output hold time from SDCLK(2:0) rise MD(31:0) read data input setup time from SDCLK(2:0) rise MD(31:0) read data input hold time from SDCLK(2:0) rise 10 1 1 2 3.8 20 ns, 2 sdclk sdclk sdclk ns, 3
tsynSDOH tsynSDIS tsynDIH
3.6 0.5 1.5
ns, 3 ns ns
Fast Flash (Synchronous READS only) tffCLK tffAS tffCES tffADV tffOS tffCEH SDCLK period MA(25:0) setup to nSDCAS (as nADV) asserted nCS setup to nSDCAS (as nADV) asserted nSDCAS (as nADV) pulse width nSDCAS (as nADV) de-assertion to nOE assertion nOE deassertion to nCS de-assertion 15 0.5 0.5 1 3 4 20 ns, 4 sdclk sdclk sdclk sdclk sdclk
NOTES: 1. These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK. 2. SDCLK for SDRAM, SMROM, and SDRAM-timing Synchronous Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be 99.5 MHz at the fastest. 3. This number represents 1/2 SDCLK period. 4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of the 132.7 MHz MEMCLK at its fastest.
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Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
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4.9
Peripheral Module AC Specifications
This section describes the AC specifications for the LCD and SSP peripheral units.
4.9.1
LCD Module AC Timing
Figure 7 describes the LCD timing parameters. The LCD pin timing specifications are referenced to the pixel clock (L_PCLK). Values for the parameters are given in Table 23.
Figure 7. LCD AC Timing Definitions
L_PCLK
Tpclkdv
L_LDD[7:0] (rise)
Tpclkdv
L_LDD[7:0] (fall) L_LCLK L_BIAS
Tpclklv Tpclkbv
L_FCLK
Tpclkfv
A4775-01
Table 23. LCD AC Timing Specifications
Symbol Tpclkdv Tpclklv Tpclkfv Tpclkbv Description Tpclkdv L_PCLK rise/fall to L_LDD<7:0> driven valid L_PCLK fall to L_LCLK driven valid L_PCLK fall to L_FCLK driven valid L_PCLK rise to L_BIAS driven valid Min 0 -0.5 -0.5 5.524 Max 3.5 2.0 2.0 12 Units ns ns ns ns Notes 1 2 2 2
NOTES: 1. Program the LCD data pins to be driven on either the rising or falling edge of the pixel clock (L_PCLK). 2. These LCD signals can, at times, transition when L_PCLK is not clocking (between frames). At this time, they are clocked with the internal version of the pixel clock before it is driven out onto the L_PCLK pin.
4.9.2
SSP Module AC Timing
Figure 8, "SSP AC Timing Definitions" on page 38 describes the SSP timing parameters. The SSP pin timing specifications are referenced to SCLK_C. Values for the parameters are given in Table 24, "SSP AC Timing Specifications" on page 38.
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Electrical Specifications
Figure 8. SSP AC Timing Definitions
SCLK_C
Tsfmv
SFRM_C
Tsfmv
TXD_C
Trxds Trxdh
RXD_C
A4774-01
Table 24. SSP AC Timing Specifications
Symbol Tsfmv Trxds Trxdh Tsfmv Description SCLK_C rise to SFRM_C driven valid RXD_C valid to SCLK_C fall (input setup) SCLK_C fall to RXD_C invalid (input hold) SCLK_C rise to TXD_C valid 11 0 22 Min Max 21 Units ns ns ns ns Notes
4.9.3
Boundary Scan Test Signal Timings
Table 25, "Boundary Scan Test Signal Timing" shows the boundary scan test signal timing.
Table 25. Boundary Scan Test Signal Timing (Sheet 1 of 2)
Symbol TBSF TBSCH TBSCL TBSCR TBSCF TBSIS1 TBSIH1 TBSIS2 TBSIH2 TBSOV1 TOF1 TOV12 Parameter TCK frequency TCK high time TCK low time TCK rise time TCK fall time Input setup to TCK TDI, TMS Input hold from TCK TDI, TMS Input setup to TCK nTRST Input hold from TCK nTRST TDO valid delay TDO float delay All outputs (non-test) valid delay 4.0 6.0 25.0 3.0 1.5 1.1 1.5 6.9 5.4 6.9 Min 0.0 15.0 15.0 5.0 5.0 Max 33.33 Units MHz ns ns ns ns ns ns ns ns ns ns ns Relative to falling edge of TCK Relative to falling edge of TCK Relative to falling edge of TCK Measured at 1.5 V Measured at 1.5 V 0.8 V to 2.0 V 2.0 V to 0.8 V Notes
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Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
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Table 25. Boundary Scan Test Signal Timing (Sheet 2 of 2)
Symbol TOF2 TIS10 TIH8 Parameter All outputs (non-test) float delay Input setup to TCK all inputs (non-test) Input hold from TCK all inputs (non-test) Min 1.1 4.0 6.0 Max 5.4 Units ns ns ns Notes Relative to falling edge of TCK
4.10
AC Test Conditions
The AC specifications in Section 4.5, "Targeted AC Specifications" on page 27 are tested with a 50 pF load indicated in Figure 9.
Figure 9. AC Test Load
Output Ball
C L = 50pF CL
Intel(R) PXA255 Processor Electrical, Mechanical, and Thermal Specification
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